Advanced Digital Design with the Verilog HDL

For an advanced course in digital design for seniors and first-year graduate students in electrical engineering, computer engineering, and computer science.
This book builds on the student's background from a first course in logic design and focuses on developing, verifying, and synthesizing designs of digital circuits. The Verilog language is introduced in an integrated, but selective manner, only as needed to support design examples (includes appendices for additional language details). It addresses the design of several important circuits used in computer systems, digital signal processing, image processing, and other applications.

Autorentext
Michael Ciletti is Professor Emeritus in the Department of Electrical and Computer Engineering at the University of Colorado, Colorado Springs. His areas of interest include  Modeling, synthesis and verification of digital systems with hardware description languages, system-level design languages, and embedded systems with FPGAs. He is the author of Advanced Digital Design with the Verilog HDL and the co-author of Digital Design, 4e.

Klappentext
For an advanced course in digital design for seniors and first-year graduate students in electrical engineering, computer engineering, and computer science. This book builds on the student's background from a first course in logic design and focuses on developing, verifying, and synthesizing designs of digital circuits. The Verilog language is introduced in an integrated, but selective manner, only as needed to support design examples (includes appendices for additional language details). It addresses the design of several important circuits used in computer systems, digital signal processing, image processing, and other applications.

Zusammenfassung
  Advanced Digital Design with the Verilog HDL, 2e, is ideal for an advanced course in digital design for seniors and first-year graduate students in electrical engineering, computer engineering, and computer science.
This book builds on the student's background from a first course in logic design and focuses on developing, verifying, and synthesizing designs of digital circuits. The Verilog language is introduced in an integrated, but selective manner, only as needed to support design examples (includes appendices for additional language details). It addresses the design of several important circuits used in computer systems, digital signal processing, image processing, and other applications.

Inhalt
1 Introduction to Digital Design Methodology 1 1.1 Design Methodology–An Introduction 1.1.1 Design Specification 1.1.2 Design Partition 1.1.3 Design Entry 1.1.4 Simulation and Functional Verification 1.1.5 Design Integration and Verification 1.1.6 Presynthesis Sign-Off 1.1.7 Gate-Level Synthesis and Technology Mapping 1.1.8 Postsynthesis Design Validation 1.1.9 Postsynthesis Timing Verification 1.1.10 Test Generation and Fault Simulation 1.1.11 Placement and Routing 1.1.12 Physical and Electrical Design Rule Checks 1.1.13 Parasitic Extraction 1.1.14 Design Sign-Off 1.2 IC Technology Options 1.3 Overview References   2 Review of Combinational Logic Design 13 2.1 Combinational Logic and Boolean Algebra 2.1.1 ASIC Library Cells 2.1.2 Boolean Algebra 2.1.3 DeMorgan’s Laws 2.2 Theorems for Boolean Algebraic Minimization 2.3 Representation of Combinational Logic 2.3.1 Sum-of-Products Representation 2.3.2 Product-of-Sums Representation 2.4 Simplification of Boolean Expressions 2.4.1 Simplification with Exclusive-Or 2.4.2 Karnaugh Maps (SOP Form) 2.4.3 Karnaugh Maps (POS Form) 2.4.4 Karnaugh Maps and Don’t-Cares 2.4.5 Extended Karnaugh Maps 2.5 Glitches and Hazards 2.5.1 Elimination of Static Hazards (SOP Form) 2.5.2 Summary: Elimination of Static Hazards in Two-Level Circuits 2.5.3 Static Hazards in Multilevel Circuits 2.5.4 Summary: Elimination of Static Hazards in Multilevel Circuits 2.5.5 Dynamic Hazards 2.6 Building Blocks for Logic Design 2.6.1 NAND—NOR Structures 2.6.2 Multiplexers 2.6.3 Demultiplexers 2.6.4 Encoders 2.6.5 Priority Encoder 2.6.6 Decoder 2.6.7 Priority Decoder References Problems   3 Fundamentals of Sequential Logic Design 69 3.1 Storage Elements 3.1.1 Latches 3.1.2 Transparent Latches 3.2 Flip-Flops 3.2.1 D-Type Flip-Flop 3.2.2 Master—Slave Flip-Flop 3.2.3 J-K Flip-Flops 3.2.4 T Flip-Flop 3.3 Busses and Three-State Devices 3.4 Design of Sequential Machines 3.5 State-Transition Graphs 3.6 Design Example: BCD to Excess-3 Code Converter 3.7 Serial-Line Code Converter for Data Transmission 3.7.1 Design Example: A Mealy-Type FSM for Serial Line-Code Conversion 3.7.2 Design Example: A Moore-Type FSM for Serial Line-Code Conversion 3.8 State Reduction and Equivalent States References Problems   4 Introduction to Logic Design with Verilog 103 4.1 Structural Models of Combinational Logic 4.1.1 Verilog Primitives and Design Encapsulation 4.1.2 Verilog Structural Models 4.1.3 Module Ports 4.1.4 Some Language Rules 4.1.5 Top-Down Design and Nested Modules 4.1.6 Design Hierarchy and Source-Code Organization 4.1.7 Vectors in Verilog 4.1.8 Structural Connectivity 4.2 Logic System, Design Verification, and Test Methodology 4.2.1 Four-Value Logic and Signal Resolution in Verilog 4.2.2 Test Methodology 4.2.3 Signal Generators for Testbenches

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