Reuse Techniques for VLSI Design

Reuse Techniques for VLSI Design is a reflection on the current state of the art in design reuse for microelectronic systems. To that end, it is the first book to garner the input of leading experts from both research and application areas. These experts document herein not only their more mature approaches, but also their latest research results.
Firstly, it sets out the background and support from international organisations that enforce System-on-a-Chip (SoC) design by reuse- oriented methodologies. This overview is followed by a number of technical presentations covering different requirements of the reuse domain. These are presented from different points of view, i.e., IP provider, IP user, designer, isolated reuse, intra-company or inter-company reuse. More general systems or case studies, e.g., metrics, are followed by comprehensive reuse systems, e.g., reuse management systems partly including business models.
Since design reuse must not be restricted to digital components, mixed- signal and analog reuse approaches are also presented. In parallel to the digital domain, this area covers research in reuse database design. Design verification and legal aspects are two important topics that are closely related to the realization of design reuse. These hot topics are covered by presentations that finalize the survey of outstanding research, development and application of design reuse for SoC design. Reuse Techniques for VLSI Design is an invaluable reference for researchers and engineers involved in VLSI/ASIC design.

Klappentext
Reuse Techniques for VLSI Design is a reflection on the current state of the art in design reuse for microelectronic systems. To that end, it is the first book to garner the input of leading experts from both research and application areas. These experts document herein not only their more mature approaches, but also their latest research results. Firstly, it sets out the background and support from international organisations that enforce System-on-a-Chip (SoC) design by reuse- oriented methodologies. This overview is followed by a number of technical presentations covering different requirements of the reuse domain. These are presented from different points of view, i.e., IP provider, IP user, designer, isolated reuse, intra-company or inter-company reuse. More general systems or case studies, e.g., metrics, are followed by comprehensive reuse systems, e.g., reuse management systems partly including business models. Since design reuse must not be restricted to digital components, mixed- signal and analog reuse approaches are also presented. In parallel to the digital domain, this area covers research in reuse database design. Design verification and legal aspects are two important topics that are closely related to the realization of design reuse. These hot topics are covered by presentations that finalize the survey of outstanding research, development and application of design reuse for SoC design. Reuse Techniques for VLSI Design is an invaluable reference for researchers and engineers involved in VLSI/ASIC design.

Inhalt
1 ECSI, VSIA and MEDEA How International Organisations Support Reusability.- 1.1 Abstract.- 1.2 The System-on-a-chip Challenge.- 1.3 ECSI The European CAD Standardisation Initiative.- 1.4 VSIA The Virtual Socket Interface Alliance.- 1.5 MEDEA The Eureka Project on Micro-Electronic Development for European Applications.- 2 Analyzing The Cost of Design for Reuse.- 2.1 Abstract.- 2.2 Introduction.- 2.3 Case Study: ATM Shaper Design.- 2.4 Specific and Reusable Blocks.- 2.5 Comparing Reusable and Specific Components.- 2.6 Conclusion.- 3 A Flexible Classification Model for Reuse of Virtual Components.- 3.1 Introduction.- 3.2 Objective.- 3.3 State of the Art.- 3.4 RMS Similarity Metric.- 3.5 The RMS-Taxonomy.- 3.6 Extended RMS-Classification.- 3.7 Implementation.- 3.8 Application of the Model.- 3.9 Conclusion and Outlook.- 4 An Integrated Approach Towards a Corporate Design Reuse Strategy.- 4.1 Introduction.- 4.2 Why is Design Reuse Difficult?.- 4.3 Core Supply Process.- 4.4 Organization.- 4.5 Business Models.- 4.6 Ensuring Core Quality.- 4.7 Technical Issues.- 4.8 The Overall Strategy.- 5 Design Methodology for IP Providers.- 5.1 How to Become an IP Vendor.- 5.2 IP Database Structure.- 5.3 Documentation of IP.- 5.4 Simulation Testbench Philosophy.- 5.5 Release Management.- 5.6 Dual Language DesignObjects.- 5.7 Scalable DesignObjects.- 5.8 Experience from Reuse Projects.- 5.9 Conclusions.- 6 Hard IP Reuse Methodology for Embedded Cores.- 6.1 Introduction.- 6.2 Simulation Model Generation.- 6.3 StarterKit Simulation Environment.- 6.4 Timing Characterization and Timing Models.- 6.5 Frontend Views and Embedded Core Test Methodologies.- 6.6 Backend Views and Backend Design.- 6.7 IP Repository.- 6.8 Next Steps.- 7 A Reuse Library Approach in Engineering Context.-7.1 Motivation.- 7.2 Project Description and Objectives.- 7.3 Reuse Methodology.- 7.4 Module Administration.- 7.5 Presentation and Access to Modules.- 7.6 Measurement.- 7.7 Summary.- 7.8 Conclusion.- 7.9 Status of the Work.- 7.10 Outlook.- 8 Aspects of Reuse in The Design of Mixed-Signal Systems.- 8.1 Abstract.- 8.2 Introduction.- 8.3 Top-Down Design Flow.- 8.4 Databases and Reuse.- 8.5 Summary.- 9 Design Reuse Experiment for Analog Modules Dream.- 9.1 Introduction.- 9.2 Requirements for Reuse of Analog Blocks.- 9.3 Implementation.- 9.4 Experience.- 9.5 Future work.- 9.6 Acknowledgement.- 10 Redesign of An MPEG-2-HDTV Video Decoder Considering Reuse Aspects.- 10.1 Introduction.- 10.2 Design Reuse.- 10.3 Redesign of an MPEG-2-HDTV Video Decoder.- 10.4 Design by Reuse (Inverse Quantiser).- 10.5 Design for Reuse (IDCT Inverse Discrete Cosine Transform).- 10.6 Summary.- 11 Reuse Concepts in Gropius.- 11.1 Abstract.- 11.2 Introduction.- 11.3 Gropius a Survey.- 11.4 Design Reuse across Abstraction Levels.- 11.5 Everything can be Abbreviated.- 11.6 Polymorphism.- 11.7 Parameterization with Circuits.- 11.8 Regularity.- 11.9 Strict Separation between Functional and Temporal Aspects.- 11.10 Uniform Communication Protocol at the System Level.- 11.11 Conclusion.- 12 Legal Aspects of Reuse of Intellectual Property.- 12.1 Issues.- 12.2 Legal Situation.- 12.3 Contractual and Technical Remedies.- 13 References.

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